Conventionally, semiconductor memory devices such as flash memory have been manufactured by two-dimensionally integrating elements on a surface of a silicon substrate. For increasing memory capacity of such a semiconductor memory device, miniaturization has been achieved by making the sizes of the individual elements smaller. However, in recent years, the miniaturization has become difficult in cost and technique.
For solving such problems, a number of ideas of three-dimensionally integrating elements have been proposed. For example, a memory device in which one-time-programmable elements are sandwiched among multilayer wirings, a memory device in which a plurality of layers of conventional NAND-type flash memories are formed by repeating epitaxial growth of silicon films, and so forth have been proposed. However, the three-dimensional devices require several times of lithography processes per layer, and therefore, even by the three-dimensionization, it is difficult to reduce the cost.
With conceiving such problems, the present inventors and others proposed a collectively processed three-dimensional stacked memory (see, for example, Patent Document 1). In this technique, a selection transistor in which a silicon pillar extending in the vertical direction serves as a channel is formed on a silicon substrate, and thereon, electrode films and insulating films are alternately stacked to form a stacked body, and then, through-holes are formed in the stacked body by collective processing. And, a charge storage layer is formed on the side surface of the through-hole, and a silicon pillar is buried inside the through-hole to be connected to the silicon pillar of the selection transistor. Thereby, a memory cell is formed in each of the intersection parts of the electrode films and the silicon pillars. In the collectively processed three-dimensional stacked memory, by controlling potentials of each of the electrode films and each of the silicon pillars, a charge can be transferred between the silicon pillar and the charge storage layer, and thereby, information can be recorded. According to this technique, the through-holes are formed by collective-processing of the stacked body, and therefore, even when the number of the stacked layers of the electrode films increases, the number of the lithography processes does not increase, and increase in cost can be suppressed.
However, in manufacturing the memory, when the silicon pillars are buried inside the through-holes, it is necessary to remove silicon oxide such as natural oxide film or the like from the bottom surfaces of the through-holes so that an electric contact between the newly buried silicon pillar and the silicon pillar constituting the channel of the selection transistor is improved. In general, before burying the silicon pillar in the through-hole, a pretreatment using a hydrofluoric acid type solution is performed. However, by the pretreatment, the charge storage layers are damaged, and the reliability of the charge storage layer comes to lower. For avoiding this problem, the charge storage layer is required to have a film structure to be resistant to the pretreatment. However, various technical restrictions emerge in this case. For example, in a case of introduction of a multi-value technique for more improving the memory density, film structures are restricted, and therefore, development of charge storage layers comes to be difficult.